[U]nless otherwise compelled . . . the same claim term in the same patent or related patents carries the same construed meaning.

On August 15, 2012, in In re Rambus Inc., the U.S. Court of Appeals for the Federal Circuit (Rader, Linn,* Dyk) affirmed the USPTO Board of Patent Appeals and Interferences decision upholding the patent examiner's rejection of the claims during a reexamination of U.S. Patent No. 6,034,918, which related to synchronous memory devices that output only a specified amount of data in response to a request. The Federal Circuit stated:

The PTO contends that the Board correctly focused its analysis on construction of the term "memory device" in claim 18 of the '918 Patent and affirmed the examiner's rejection based on a construction of this term as meaning a "device[] that allows for the electronic storage and retrieval of information." . . . Rambus, on the other hand, argues that the Board erred because a "memory device" has two relevant limitations: (1) it is a single chip component and (2) it does not have a memory controller. Rambus disputes the examiner's and Board's construction because the Board considered each word individually and then construed the phrase to cover "multiple electronic appliances grouped together, that allow[] information to be stored and retrieved." According to Rambus, this broad construction makes no sense in the context of the '918 Patent. Instead, Rambus would define the term "memory device" as necessarily consisting of only one chip with no control function, and would not define the term by what its two component words individually mean.

Rambus relies on language from the specification, expert testimony, and the prosecution history of the '918 Patent to support its argument that a "memory device" must be a single chip device. . . . This court agrees with the Board that the specification does not restrict the invention to single chip memory devices. There are no words of manifest exclusion or clear disavowals of multichip devices -- there are only preferred embodiments and goals of the invention that Rambus argues are better met by single chip devices. The specification language Rambus cites shows only that the invention can be carried out with a single chip memory device, it does not require the invention to be so performed. Other portions of the specification that Rambus cites are completely inapposite to the determination of the number of chips in a memory device. Rambus stresses that the invention allows "high-speed access to large blocks of data from a single memory device." But this in no way indicates that the single memory device must be made of a single memory chip.

Rambus has not demonstrated that a "memory device" is a term of art, and nothing indicates these other "devices" are limited to single chips. To the extent Rambus wanted to limit the memory device to a single chip component, it could have expressly done so. It did not, and this court will not do so here. . . . In sum, "memory device" is a broad term which has been used consistently in the '918 patent and in the family of patents related to it to encompass a device having one or more chips. [T]here is no basis to find a disavowal or redefinition that would limit the term "memory device" to a single chip. Rambus also disagrees with the examiner's construction of the term "memory device" as encompassing devices that perform a control function. . . . Rambus argues that the term memory device cannot include a memory controller. [The PTO] argues that the specification makes clear that the '918 Patent's memory device includes functions like those performed by the iAPX manual's MCU. The PTO also agrees with the district court's conclusion that the memory device can, and indeed must, provide at least the control functionality necessary to enable the memory chip or chips to interface with the rest of the system, similar to how the MCU controls the array in the iAPX Manual. The PTO argues this is true even if the argument to overcome Jackson resulted in a disclaimer of a CPU or global bus controller.

We agree with the PTO. Rambus's construction broadly excluding any memory controller that provides more functionality than simple control logic fails. First, claim 18 itself does not limit any "control" function that the memory device might carry out. In fact, the claim expressly calls for the memory device to provide the control functionality of receiving block size requests and outputting specific amounts of data. Nothing in the claim prevents the memory device from consisting of a storage chip and a device that facilitates the receiving and outputting from that storage chip. And at oral argument Rambus conceded that the memory device must at minimum have such control logic. Rambus only attempted to exclude more complex controllers from the memory device. But excluding more complex controllers does not eliminate all control functionality.

[T]he general speed and efficiency goals Rambus relies on do not require a construction of "memory device" that excludes all control functionality. Pursuant to claim 18, the memory device needs only to receive and output specific data, functions it can perform even while exhibiting other minor functionality, without wholly defeating the invention's speed and efficiency goals. And while Rambus did exclude the functions of Jackson's BIU during prosecution, this restriction only prevents the memory device from containing a global bus controller or CPU, not from containing a component that interfaces with the computer system, even when that component provides some additional functionality.

Finally, Rambus admits that a key part of the '918 Patent's invention was a device with "'all the functionality' of prior art memory boards." Thus, a memory device is not just a functionless storage chip. The memory device must have some functionality -- specifically the data receiving and outputting functions described in claim 18. Thus, consistent with the specification, prosecution history, and the Micron district court's construction, we construe a "memory device" as a component of a memory subsystem, not limited to a single chip, where the device may have a controller that, at least, provides the logic necessary to receive and output specific data, but does not perform the control function of a CPU or bus controller.

The parties entire anticipation dispute turns on whether the memory device in claim 18 of the '918 Patent reads on the memory module in the iAPX Manual. We conclude that substantial evidence supports the Board's decision that it does. The Board accepted Rambus's characterization of the iAPX Manual's module as "contain[ing] at least 12 TTL packaged chips, a memory controller chip, and several DRAM chips" without further comment on the examiner's control function analysis. Correctly construed, the "memory device" described in claim 18 of the '918 Patent can contain more than one chip and may contain a controller that provides the logic necessary for the memory device to receive and output specific data, but that controller does not function like a CPU. Rambus agreed at oral argument that the MCU in the memory module of the iAPX Manual provided the necessary logic, but tried to distinguish the MCU because it "does more than that." But as the examiner recognized, it is the bus controller (i.e., the "BIU") of the iAPX that is akin to the BIU that Rambus distinguished during prosecution, not the local "MCU" that is within iAPX's "memory module." There is no suggestion that the BIU of the iAPX is within the memory module, rather it is clearly outside of the memory module, thus satisfying the requirement that the memory module receive a request from a bus controller. By not restricting a memory device to a single chip or otherwise restricting the necessary interface control logic function within the claims, there is simply no principled way to distinguish the iAPX Manual's memory module, which contains several chips and a controller that provides the logic for those chips to function, from the '918 Patent's memory device. Thus, substantial evidence supports the Board's conclusion that the iAPX memory module reads directly on the '918 Patent's memory device.