On July 15, 2016, ALJ Thomas B. Pender issued Order No. 42 construing disputed terms of the asserted patents in Certain Computing or Graphics Systems, Components Thereof, and Vehicles Containing Same (Inv. No. 337-TA-984).
By way of background, this investigation is based on a December 28, 2015 complaint filed by Advanced Silicon Technologies LLC (“AST”) alleging violation of Section 337 in the importation and sale of certain computing or graphics systems, components thereof, and vehicles containing same that infringe one or more claims of U.S. Patent Nos. 6,339,428 (“the ’428 patent”); 6,546,439; (“the ’439 patent); 6,630,935; (“the ’935 patent”); and 8,933,945 (“the ’945 patent”). See our December 29, 2015 and January 29, 2016 posts for more details on the complaint and Notice of Investigation, respectively.
According to the order, the parties came to an agreement on the meaning of certain terms, and AST dropped certain claims during the course of the investigation. As a result, the ALJ only ruled on five disputed terms in the ’428 and ’935 patents.
The first disputed term is “texture address module” recited in claims 1 and 10 of the ’428 patent. AST argued that this term has a plain and ordinary meaning that connotes structure to one of ordinary skill in the art (e.g., texture circuitry), and should not be construed as a means-plus-function element. AST also asserted that the claim language requiring the texture address module to be operably coupled to circuit elements—including the cache and the memory—shows that “it too must be a circuit element.” Respondents countered that “texture address module” does not have a well-understood structural meaning in the video graphics field and should be construed as a means-plus-function element, and further, that the term is indefinite because the specification does not disclose sufficient structure to perform the recited functions. The Commission Investigative Staff (OUII) agreed with Respondents that “texture address” module does not have a plain and ordinary meaning and should be construed as a means-plus-function element, but argued that the specification discloses sufficient structure for performing the recited functions. The ALJ determined to give this term its plain and ordinary meaning, stating that no further construction was necessary.
The second disputed term is “arbitration module” recited in claim 1 of the ’935 patent. Like the texture address module in the ‘428 patent, the parties disputed whether “arbitration module” is a means-plus-function element, and if so, whether the specification describes sufficient structure for that element. AST argued that this term should be given its plain and ordinary meaning and need not be construed because the arbitration module is circuitry. Respondents and OUII both asserted that this term is a means-plus-function element, but disagreed as to whether it was indefinite—Respondents argued that the specification does not disclose sufficient structure to perform the recited functions of the arbitration module, whereas OUII said that it does. The ALJ determined to give this term its plain and ordinary meaning, stating that no further construction was necessary.
The third disputed term is “operation code” recited in claims 1 and 7 of the ’935 patent. AST and OUII argued that this term would be readily understood by one of ordinary skill in the art and therefore should be given its plain and ordinary meaning. Respondents, however, sought a narrower construction and argued that the inventors “deviated from the ordinary meaning of ‘operation code’ by defining the term in their invention to include more than just the operation to be performed.” Specifically, Respondents asserted that the operation code must include a thread identifier that identifies the particular thread controller that issued the instruction, a type of operation to be performed, a first and second source address, and a destination address. The ALJ rejected Respondents’ argument and agreed with AST and OUII that this term should be given its plain and ordinary meaning. The ALJ further noted that there is no dispute between the parties as to that plain and ordinary meaning (citing the following definition of “opcode” in The IEEE Standard Dictionary of Electrical and Electronic Terms: “[a] bit pattern that identifies a particular instruction”), and thus found that “operation code” requires no further construction.
The fourth disputed term is “computation engine” recited in claim 1 of the ’935 patent. Here, Respondents and OUII argued for plain and ordinary meaning while AST sought to limit this term to “specialized graphics circuitry” on the grounds that the inventors distinguished the claimed computation engine over general purpose CPU’s in the prior art that execute software. The ALJ rejected AST’s argument and construed this term according to its plain and ordinary meaning, stating that no further construction is necessary.
The fifth disputed term is the phrase “in an order to minimize idle time of the computation engine” recited in claim 1 of the ’935 patent. The parties essentially disputed whether the word “minimize” means “reduce” and therefore the idle time should be compared to an unprioritized scheme (e.g., where items are submitted to the computation engine in serial fashion), or whether it means “reduce to the smallest possible amount” and therefore the idle time should be compared to every other possible prioritized or unprioritized scheme. Respondents and the OUII argued for the latter approach, and believed that because the specification and prosecution history provide no guidance or objective boundaries for determining whether idle time has been “reduced to the smallest possible amount,” the disputed phrase is indefinite. The ALJ disagreed, however, and adopted the following alternative construction proposed by OUII: “in a sequence that minimizes idle time of the computation engine relative to without an application specific prioritization scheme.”
Finally, the ALJ agreed with AST’s definition of a person of ordinary skill in the art found that such a person would have a Bachelor’s degree in electrical engineering, computer engineering, computer science, or an equivalent field as well as at least three years of academic or industry experience in memory systems technology, computer architecture, or comparable industry experience.