Protecting semiconductor device and fabrication process inventions can be challenging. This is because showing that such inventions are being used by others often requires reverse engineering, a process that is costly and time consuming and that may not even show that an invention is being used. Patent drafters who do not fully understand the underlying technology can thus make enforcement of valuable semiconductor IP very difficult. We discuss below several issues relating to semiconductor patent enforcement, and several factors to consider when drafting semiconductor patent applications with an eye towards enforcement.

To enforce a patent, a patent owner needs to show that an accused product or process meets each element of a patent claim. For example, if a semiconductor device claim recites: "a metal-oxide-semiconductor device including: a source; a drain; and a gate structure," to show infringement, the accused product must include a device made of metal, oxide, and semiconductor, and must also include a source, a drain, and a gate structure.

The nature of semiconductor devices presents enforcement challenges because such devices are manufactured in nanometer scale, and often built in a multilayer structure, making any analysis of infringing products very time-consuming and costly. Showing infringement of a nanoscale, multilayer semiconductor device including a gate structure may require multiple high-resolution cross-sectional scanning electron microscope (SEM) and transmission electron microscope (TEM) analyses. In addition, multiple metal layers from the back end of line (BEOL) process may have to be removed by etching processes if a plan view of the gate structure is required.

Additionally certain features may require increased time and cost in the reverse engineering process. Assume that the previous claim example is modified and the claim recites "a polysilicon gate structure having a phosphorus doping concentration of 1E20/cm3," instead of simply "a gate structure." In addition to SEM, TEM, and etching processes, other analyses may be necessary, such as energy dispersive xray spectroscopy (EDS) and secondary ion mass spectrometry (SIMS). The cost of these reverse engineering analyses can be tens of thousands of dollars (or more), depending what the claim recites.  The time and cost of proving patent infringement can be exacerbated by claims that are unnecessarily specific or unclear, sometimes the result of a patent drafter unfamiliar with the technology. Further, oftentimes a patent owner will need to analyze a large portfolio of devices to identify infringing products. All of the above may make a patent supposedly protecting a critical invention very difficult to enforce. Furthermore, reasonable pre-suit investigation of infringement is required, which means that costly reverse engineering may be necessary before an enforcement action can be brought. Thus, reverse engineering potentially infringing products is often a necessary step of enforcing a semiconductor patent.  To mitigate the challenges and costs discussed above, semiconductor patent applications should be drafted by practitioners familiar with the technology and who are more likely to understand whether certain features can be easily identified in infringing products. Furthermore, a knowledgeable draftsman may be able to write patent claims that best protect the invention without being overly difficult to prove.

A couple of factors affecting the identification of claim features using reverse engineering, often overlooked, should be considered when drafting claims. First, when drafting a semiconductor process claim, one should pay additional attention to subtractive steps in a semiconductor fabrication process, e.g., an etching process. For example, if a layer is entirely removed/etched, it may not be straightforward to show the layer ever existed or an etching process was performed by just analyzing the finished product. This will make it difficult to prove a claimed process is used when considering the end product. And detailed steps in fabrication processes are likely not published and may be protected as trade secrets.

Second, the analytical capabilities of the tools used for reverse engineering (such as spectroscopy and electron microscope) have limits. They often determine which feature can be identified through reverse engineering in an infringing product, which may, in turn, determine what features can be included in a claim. Intuitively, qualitative analysis (e.g., existence of a certain phosphorus in a semiconductor layer) is less challenging than quantitative analysis (e.g., concentration of phosphorus). A patent agent or attorney should understand the analytical limits of reverse engineering techniques in order to draft patent claims that can be shown to be used.

There are unique challenges to drafting and enforcing semiconductor patents because of their miniature nature and complicated fabrication processes and the use of highly-technical and expensive reverse engineering analyses to show infringement. Semiconductor patent applications should be drafted by those familiar with the technology and limits of reverse engineering analyses to best protect such inventions.

Originally printed in ECN Magazine.